Development and Validation of a Hierarchical Memory Model Incorporating CPU- and Memory-Operation Overlap

In this paper, we characterize application performance with a "memory-centric" view. Using a simple strategy and performance data measured on actual machines, we model the performance of a simple memory hierarchy and infer the contribution of each level in the memory system to an application's overall cycles per instruction (cpi). Included are results affirming the usefulness of the memory model over several platforms, namely the SGI Origin 2000, SGI PowerChallenge, and the Intel ASCI Red TFLOPS supercomputers. We account for the overlap of processor execution with memory accesses a key parameter, which is not directly measurable on most systems. Given the system similarities between the Origin 2000 and the PowerChallenge, we infer the separate contributions of three major architecture features in the memory subsystem of the Origin 2000: cache size, outstanding loads-under-miss, and memory latency.